*******************************************************************************
****** Top_3 schematic FINAL  <vs>  Top_3 layout FINAL
*******************************************************************************

Filter/Reduce statistics only. Network matching was OK.
                                                                                                                                                                   
Pre-expand Statistics                      
======================                          Original       
Cell/Device                               schematic  layout
(OUTPUT_PAD_buff schematic ICGTRG...) Cell        5       5
(BONDPAD schematic ICGTRGRE, BONDPAD) Cell       16      10*
(subc) Generic                                    1       3*
(INPUT_PAD_buff_Bz schematic FINA...) Cell       11       2*
(power_stage_cap schematic FINAL,...) Cell        1       1
(Core_LVS schematic vlsifinal, _) Cell            1       0*
(_, M1_MA layout ICGTROPT_UTILS) Cell             0       2*
(_, Core_4 layout vlsifinal) Cell                 0       1*
(_, E1_MA symbolic cmrf8sf column...) Cell        0       2*
(_, INPUT_PAD_buff layout ICGTRGRE) Cell          0       2*
(_, INPUT_PAD_buff_VAR2 layout IC...) Cell        0       6*
(_, INPUT_PAD_buff_VAR1 layout IC...) Cell        0       1*
                                             ------  ------
Total                                            35      35

Filter Statistics
=================                               Original            Filtered
Cell/Device                               schematic  layout   schematic  layout
(Dead_Time_full) Cell                            15      15          15      15
(OUTPUT_PAD_buff) Cell                            5       5           5       5
(comparator_layout) Cell                          1       1           1       1
(peng_final) Cell                                 1       1           1       1
(power_stage) Cell                                1       1           1       1
(power_stage_cap) Cell                            1       1           1       1
(bondpad) Generic                                 0       0           0       0
(bondpad_m0) Generic                             27      27          22      22
(esdndsx) Generic                                 0       0           0       0
(esdndsx_m0) Generic                             22      44*         22      44*
(esdvpnp) Generic                                 0       0           0       0
(esdvpnp_m0) Generic                             22      22          22      22
(nfet) Generic                                    0       0           0       0
(nfet_m0) Generic                                55     242*         55     242*
(nfet_m1) Generic                                11      33*         11      33*
(opppcres) Generic                                0       0           0       0
(opppcres_m0) Generic                            11      11          11      11
(pfet) Generic                                    0       0           0       0
(pfet_m0) Generic                                55     242*         55     242*
(pfet_m1) Generic                                11      33*         11      33*
(subc) Generic                                   61      35*         61      35*

Reduce Statistics
=================                               Filtered             Reduced
Cell/Device                               schematic  layout   schematic  layout
(Dead_Time_full) Cell                            15      15          15      15
(OUTPUT_PAD_buff) Cell                            5       5           5       5
(comparator_layout) Cell                          1       1           1       1
(peng_final) Cell                                 1       1           1       1
(power_stage) Cell                                1       1           1       1
(power_stage_cap) Cell                            1       1           1       1
(bondpad) Generic                                 0       0           0       0
(bondpad_m0) Generic                             22      22          22      22
(esdndsx) Generic                                 0       0           0       0
(esdndsx_m0) Generic                             22      44*         22      22
(esdvpnp) Generic                                 0       0           0       0
(esdvpnp_m0) Generic                             22      22          22      22
(nfet) Generic                                    0       0           0       0
(nfet_m0) Generic                                55     242*         55      55
(nfet_m1) Generic                                11      33*         11      11
(opppcres) Generic                                0       0           0       0
(opppcres_m0) Generic                            11      11          11      11
(pfet) Generic                                    0       0           0       0
(pfet_m0) Generic                                55     242*         55      55
(pfet_m1) Generic                                11      33*         11      11
(subc) Generic                                   61      35*          1       1
                                             ------  ------      ------  ------
Total                                           294     708         234     234

Schematic and Layout Match