Luke Wang
Department of Electrical and Computer Engineering
University of Toronto
Bahen Centre
40 St.George Street
Room 5000
Toronto, ON M5S 2E4

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I obtained a BASc in Electrical Engineering from University of Waterloo in 2011 and a MASc for my work on timing skew calibration for time-interleaved ADCs from University of Toronto in 2014. I worked on a 28nm SERDES project while interning at Broadcom from July to October 2013. I am currently pursuing a PhD degree at University of Toronto under the supervision of Professor Anthony Chan Carusone.


A full CV can be found here.

Research Interests

Analog circuit design for wireline communication and adaptive digital signal processing.


NSERC Postgraduate Scholarship (PGS D) (2015-2018)
Ontario Graduate Scholarship (2014-2015)
Queen Elizabeth II/ISS '97 Scholarship in Science and Technology (2012-2013)
NSERC Alexander Graham Bell Canada Graduate Scholarship (CGS M) (2011-2012)
University of Waterloo President's Research Award (2009)
University of Waterloo President's Scholarship (2006)
University of Waterloo Nortel Networks Award (2006)
University of Waterloo Dean's Honours List (2006-2011)


L. Wang and A.Yasotharan, "FPGA-based QR decomposition signal processor for GPS anti-jamming array antenna", Tech. Memo TM 2009-025, DRDC Ottawa, Nov. 2009.
L. Wang, Q. Wang, A. Chan Carusone, "Time Interleaved C-2C SAR ADC with Background Timing Skew Calibration in 65nm CMOS", ESSCIRC, Sept. 2014.