Luke Wang
Department of Electrical and Computer Engineering
University of Toronto
Bahen Centre
40 St.George Street
Room 5000
Toronto, ON M5S 2E4

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I obtained a BASc in Electrical Engineering from University of Waterloo in 2011 and a MASc for my work on timing skew calibration for time-interleaved ADCs from University of Toronto in 2014. I worked on a 28nm SERDES project while interning at Broadcom from July to October 2013. I am currently pursuing a PhD degree at University of Toronto under the supervision of Professor Anthony Chan Carusone and in collaboration with Huawei Canada.


A full CV can be found here.

Research Interests

Analog circuit design for wireline communication and adaptive digital signal processing.


Edward Rogers Sr. Graduate Scholarship (2017)
NSERC Postgraduate Scholarship (PGS D) (2015-2018)
Ontario Graduate Scholarship (2014-2015)
Queen Elizabeth II/ISS '97 Scholarship in Science and Technology (2012-2013)
NSERC Alexander Graham Bell Canada Graduate Scholarship (CGS M) (2011-2012)
University of Waterloo President's Research Award (2009)
University of Waterloo President's Scholarship (2006)
University of Waterloo Nortel Networks Award (2006)
University of Waterloo Dean's Honours List (2006-2011)


L. Wang, Y. Fu, M. LaCroix, E. Chong, A. Chan Carusone, "A 64Gb/s PAM-4 Transceiver Utilizing an Adaptive Threshold ADC in 16nm FinFET," International Solid State Circuits Conference, Feb. 11-15, 2018.
L. Wang, M. LaCroix, A. Chan Carusone, "A 4GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16nm FinFET," IEEE Transactions on Circuits and Systems II, 2017.
L. Wang, M. LaCroix, A. Chan Carusone, "A 4GS/s Reconfigurable Folding Flash ADC for Time Interleaving in 16nm FinFET," International Symposium on Circuits and Systems (Late Breaking News), Baltimore, Maryland, May 2017.
S. Chen, L. Wang, H. Zhang, R. Murugesu, D. Dunwell, A. Chan Carusone, "All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters," IEEE Transactions on VLSI Systems, 2017.
L. Wang, Q. Wang, A. Chan Carusone, "Time Interleaved C-2C SAR ADC with Background Timing Skew Calibration in 65nm CMOS", European Solid-State Circuits Conference, Sept. 2014.
L. Wang and A.Yasotharan, "FPGA-based QR decomposition signal processor for GPS anti-jamming array antenna", Tech. Memo TM 2009-025, DRDC Ottawa, Nov. 2009.