Submitted
D. Jarrett-Amor and T.C. Carusone "Simultaneous Bidirectional Signaling for Die-to-Die Links: Signal Integrity Challenges and Hybrid Circuits," invited paper IEEE Open Journal of the Solid-State Circuits Society (submitted August 29, 2024).
Publications
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D. Jarrett-Amor and T.C. Carusone, "A Comparison Between Single-Ended, NRZ Unidirectional Signaling and Single-Ended, NRZ Simultaneous-Bidirectional Signaling for Die-to-Die Links," in IEEE Micro, doi: 10.1109/MM.2024.3436008.
- D. Jarrett-Amor and T. C. Carusone, “A 16 Gbps, 0.126 pJ/bit, Single-Ended TIA Driver with Impedance Peaking Control for SBD D2D Links.” 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS), Sherbrooke, QC, Canada, 2024, pp. 45-49, doi: 10.1109/NewCAS58973.2024.10666365.
- D. Jarrett-Amor, K. Yadav, D. Zhang, B. Yang, S. Jalali, and T. C. Carusone,“A 32 Gb/s, 0.42 pJ/bit Passive Hybrid Simultaneous Bidirectional Transceiver for Die-to-Die Links,”in 2023 IEEE International Symposium on Circuits and Systems (ISCAS), May 2023, pp. 1-5. doi: 10.1109/ISCAS46773.2023.10181991.
- D. Jarrett-Amor, and F. Yuan "Low-power integrating frequency difference-to-voltage converter with applications in injection-locked FLL," Analog Integrated Circuits and Signal Processing, vol. 95, no. 1, pp. 53-65, Apr. 2018.
- D. Jarrett-Amor, and F. Yuan, "Data Transient Insensitive Phase-Locked Loops," Proc. IEEE NEW Circuits and Systems, pp.1-4, Vancouver, 2016.
- D. Jarrett-Amor, Y. J. Park, and F. Yuan, Time-Mode Techniques for Fast-Locking Phase-Locked Loops," Proc. IEEE Int'l Symp. Circuits and Systems, pp.1790-1793, Montreal, 2016.
- Y. J. Park, D. Jarrett-Amor, and F. Yuan, "Time Integrator for Mixed-Mode Signal Processing," Proc. IEEE Int'l Symp. Circuits and Systems, pp. 816-829, Montreal, 2016.
Links